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Creating Jazelle as an Extension on RISC-V |
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lolpro11:
Hello Everybody! I was reading a thesis on Java execution on hardware and read this: The hardware bytecode decoder logic is implemented in less than 12K gates. Since that seems relatively easy, (compared to other CPU extensions), I would like to try to replicate it on RISC-V. However, I don't know what the thesis' author was citing "ARM. Jazelle – ARM Architecture Extensions for Java Applications. whitepaper." I can't find it anywhere on the internet. I think it's a private paper, but I think I can access it through my uni. If anyone knows the DOI, please let me know. Thanks! https://hackspire.org/index.php/Jazelle |
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