Author Topic: Opcodes that should have been incorporated into the Z80 processor  (Read 12883 times)

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Offline willrandship

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Re: Opcodes that should have been incorporated into the Z80 processor
« Reply #30 on: February 09, 2013, 09:39:13 am »
Well, depending on how much backwards compatibility require, you could technically say that the advancement in processor design IS that process.

Heck, there's even an improved CPU called the ez80. Backwards compatible mode, but also its own instruction set, and it goes up into 50 MHz.

Offline Streetwalrus

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Re: Opcodes that should have been incorporated into the Z80 processor
« Reply #31 on: February 09, 2013, 09:45:06 am »
And it is 4 times faster at the same frequency !

Offline willrandship

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Re: Opcodes that should have been incorporated into the Z80 processor
« Reply #32 on: February 10, 2013, 09:21:45 am »
That's true too. Thanks to a faster opcode caller or something, right?

Offline Streetwalrus

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Re: Opcodes that should have been incorporated into the Z80 processor
« Reply #33 on: February 11, 2013, 04:20:40 am »
I don't know the in depth details, sorry. :s

Offline chickendude

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Re: Opcodes that should have been incorporated into the Z80 processor
« Reply #34 on: February 11, 2013, 07:15:08 am »
I believe on the ez80 instructions all generally fit into one t-state, or rather due to the way the ez80 is set up it can pipeline/decode instructions in advance and execute them within one t-state. On the z80, each cycle takes 3-6 t-states and i assume it's basically the same on the ez80. For example:
xor a takes one machine cycle of 4 t-states.
add a,3 takes two machine cycles, the first is 4 t-states and the second is 3, altogether 7 t-states.
add hl,de takes three machine cycles, the first two are 4 t-states and the third is 3, altogether 11 t-states.
add ix,de takes four machine cycles, three cycles of 4 t-states and the last one is 3, altogether 15 t-states.
ld (ix+4),a takes 5 M cycles, 4 t-states for the IX prefix, 4 more to read the opcode, 3 t-states to read the offset, 5 to add the offset and read a, 3 t-states to write a to the address.
rl (ix) takes six M cycles, amounting to 23 t-states. I'm not sure what each each cycle amounts to, i think first you've got the IX prefix (4 t-states), then the opcode (4 t-states), then the offset (here, +0, 3 t-states), i don't know what the others might be.

So i think on the ez80, these M cycles will be prefetched/decoded while the previous instruction/cycle decodes/executes (each instruction must be fetched, decoded, then executed) so that they can be immediately executed when the previous instruction ends.

EDIT: Also, i was just thinking about how convenient add hl,imm16 would've been. It'd save you from having to destroy bc/de.
« Last Edit: February 11, 2013, 07:17:34 am by chickendude »

Offline Xeda112358

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Re: Opcodes that should have been incorporated into the Z80 processor
« Reply #35 on: February 11, 2013, 07:27:25 am »
Yes, add, sub, adc, and sbc with hl for immediate values would have been nice o.o

Offline Pekka422

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Re: Opcodes that should have been incorporated into the Z80 processor
« Reply #36 on: March 29, 2013, 07:38:39 am »
I really like writing assembly for my hobby Z80 (actually, currently Z180) and have done that for a while; I have something like 40000 lines of ASM code in my system. And yes, I also have wondered what kind of added instructions would be most benficial, for ASM-coding and for compiler (another language I'm using is BASIC, and of course I have implemented a compiler for it).

So, here some of the instructions, which are appearing all the time in my existing code, or which I would consider usefull implemented as single byte opcodes (there are something like 7 to 11 single byte opcodes, which no-one or at least I am not using)

LD    rr,(HL)      where rr=BC, DE, HL
LD    (HL),ss     where ss=BC or DE
INC2  HL          same as INC HL two times
DEC2 HL

These are appearing so often, that in my assembler I have created pseudo-opcodes like LD DE,(HL)++  or LD HL,(HL).

For the compiler I would like to have following two single byte opcodes:

LD    DE,(nn)     where nn is 16 bit memory address
LD    HL,SP+s    i.e. HL gets the sum of SP and an 8-bit signed constanst; usefull not only for allocating/deallocating space from stack, but also building a reference to a variable in stack.

And what Z80 is really missing, is couple of indexing registers besides the IX and IY; so I would allocate two of the available single byte opcodes to prefixes for handling these new registers.

Another area where Z80 is lacking, is 16-bit operations. I really would like to have instructions like LD DE,(IX+n) implemented with just 3 bytes, instead of the current 6 bytes (I have also these pseudo-opcodes in my assembler, however, the saving in memory usage would really be wellcome). And yeah, there are a few other opcodes, which would be rather useful...



Offline chickendude

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Re: Opcodes that should have been incorporated into the Z80 processor
« Reply #37 on: March 29, 2013, 07:55:13 am »
I never even realized that loading 16 bit addresses into bc/de took up 4 bytes instead of 3! And i think we've all wished for a ld rr,(hl) instruction.

As for the index registers, they are just so big and slow, sometimes they're nice just 'cuz it makes your code so much more organized (or you've just run out of registers), but generally i try to stay away from them. One nice side effect of that is that i can easily keep a value in ix (or iy) without worrying about it getting changed, since i almost never use it.

Offline TIfanx1999

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Re: Opcodes that should have been incorporated into the Z80 processor
« Reply #38 on: March 29, 2013, 08:15:05 am »
Hey Pekka, welcome to Omnimaga! You should head over and <a href=http://www.omnimaga.org/index.php?board=10.0>introduce yourself</a>.
« Last Edit: March 29, 2013, 08:15:33 am by Art_of_camelot »

Offline Xeda112358

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Re: Opcodes that should have been incorporated into the Z80 processor
« Reply #39 on: August 12, 2013, 11:12:14 am »
I am in need of a subdr instruction right now :P That would let me subtract a big endian number from another.
Also, subir, addir, adddr would be nice. In fact, a bunch of instructions with increment/repeat or decrement/repeat would be nice. You could OR two buffers with:
Code: [Select]
ld hl,gbuf
 ld de,backbuf
 ld bc,768
 orir
Or shift a buffer right:
Code: [Select]
ld b,0
 ld d,64
 ld hl,gbuf
 ld c,12 \ srlir \ dec d \ jr nz,$-5

Offline willrandship

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Re: Opcodes that should have been incorporated into the Z80 processor
« Reply #40 on: August 14, 2013, 11:03:03 pm »
Well, there's always the ability to treat any part of RAM like an accumulator register. That's very handy in the ez8.