Author Topic: Casio Prizm documentation  (Read 156072 times)

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Re: Re: Casio Prizm documentation
« Reply #630 on: October 20, 2012, 05:32:01 pm »
Nice :D

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Offline fxdev

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Re: Casio Prizm documentation
« Reply #632 on: March 12, 2013, 05:46:43 pm »
I took a small look into the emulator MPU DLLs and have made a listing of modules not described in the SH7705 and SH7724 PDFs.

SH7291 (2003 - 2011)
- FLCTL NAND Flash Controller
- Cmod C-specification module
- 64k or 256k boot code ROM

SH7337 (2005 - 2009)
- FLCTL NAND Flash Controller
- AIF Audio Controller
- SD Card Controller for SDSC
- Cmod C-specification module

SH7355 (2009 - 2011)
- Similar to SH7337
- No further information is known

SH7305 (2011 - current)
- FLCTL NAND Flash Controller with ECC
- SPU2 Sound Processing Unit
- SD Card Controller for SDHC
- Cmod C-specification module
- Cmod2A C-specification module

FLCTL seems to be described in the SH7780 PDF and its technical update.
FLCTL with ECC could be the one described in the SH7786 PDF.
SD Card Controller is under NDA.
SPU2 is under NDA, so should the AIF Audio Controller.
Cmod contains the Casio-specific extensions and is under NDA.

The sound units might be a hint towards Casio's electronic dictionaries. Thus, the SH7355 (based on SH7705) may have components not relevant to calculators, and continues to function like an SH7337 on these machines.

Concerning the Casio modules themselves, here is a list of registers:

CPU7291.DLL -- from PV-S1600 SDK -- based on SH7705
Code: [Select]
0003B0E0   43 6D 6F 64 00 43 2D 73  70 65 63 69 66 69 63 61   Cmod C-specifica
0003B0F0   74 69 6F 6E 20 6D 6F 64  75 6C 65 00 44 44 43 4C   tion module DDCL
0003B100   4B 52 30 00 45 78 74 65  72 6E 61 6C 20 43 4C 4B   KR0 External CLK
0003B110   31 20 73 65 74 74 69 6E  67 00 44 44 43 4C 4B 52   1 setting DDCLKR
0003B120   31 00 45 78 74 65 72 6E  61 6C 20 43 4C 4B 32 20   1 External CLK2
0003B130   73 65 74 74 69 6E 67 00  44 44 43 4C 4B 52 32 00   setting DDCLKR2
0003B140   45 78 74 65 72 6E 61 6C  20 43 4C 4B 33 20 73 65   External CLK3 se
0003B150   74 74 69 6E 67 00 44 44  43 4B 5F 43 4E 54 52 00   tting DDCK_CNTR
0003B160   45 78 74 65 72 6E 61 6C  20 63 6C 6F 63 6B 20 63   External clock c
0003B170   6F 6E 74 72 6F 6C 00 44  44 43 53 5F 43 4E 54 52   ontrol DDCS_CNTR
0003B180   00 45 78 74 65 72 6E 61  6C 20 43 53 20 63 6F 6E    External CS con
0003B190   74 72 6F 6C 00 48 49 5A  5F 43 4E 54 52 00 49 6E   trol HIZ_CNTR In
0003B1A0   74 65 72 72 75 70 74 20  70 69 6E 20 6C 65 76 65   terrupt pin leve
0003B1B0   6C 20 63 6F 6E 74 72 6F  6C 00 46 41 53 43 52 00   l control FASCR
0003B1C0   42 43 44 20 43 61 6C 63  75 6C 61 74 69 6F 6E 20   BCD Calculation
0003B1D0   63 6F 6E 74 72 6F 6C 00  46 41 53 53 52 41 00 42   control FASSRA B
0003B1E0   43 44 20 43 61 6C 63 75  6C 61 74 69 6F 6E 20 73   CD Calculation s
0003B1F0   6F 75 72 63 65 20 41 00  46 41 53 53 52 42 00 42   ource A FASSRB B
0003B200   43 44 20 43 61 6C 63 75  6C 61 74 69 6F 6E 20 73   CD Calculation s
0003B210   6F 75 72 63 65 20 42 00  46 41 53 44 52 00 42 43   ource B FASDR BC
0003B220   44 20 43 61 6C 63 75 6C  61 74 69 6F 6E 20 72 65   D Calculation re
0003B230   73 75 6C 74 00 53 43 4F  4C 43 52 00 53 43 20 4F   sult SCOLCR SC O
0003B240   75 74 70 75 74 20 6C 65  76 65 6C 20 63 6F 6E 74   utput level cont
0003B250   72 6F 6C 00 52 54 43 53  54 52 00 52 54 43 20 43   rol RTCSTR RTC C
0003B260   6C 6F 63 6B 20 74 69 6D  65 72 20 73 74 61 72 74   lock timer start
0003B270   00 52 54 43 43 52 00 52  54 43 20 43 6C 6F 63 6B    RTCCR RTC Clock
0003B280   20 74 69 6D 65 72 20 63  6F 6E 74 72 6F 6C 00 52    timer control R
0003B290   54 43 43 4F 52 00 52 54  43 20 43 6C 6F 63 6B 20   TCCOR RTC Clock
0003B2A0   74 69 6D 65 72 20 63 6F  6E 73 74 61 6E 74 00 52   timer constant R
0003B2B0   54 43 43 4E 54 00 52 54  43 20 43 6C 6F 63 6B 20   TCCNT RTC Clock
0003B2C0   74 69 6D 65 72 20 63 6F  75 6E 74 65 72 00 00 00   timer counter

CPU7337.DLL -- from fx-9860G/GII emulator -- based on SH7705
Code: [Select]
Cmod functionality from CPU7291.DLL + OPCR Output pin control

CPU7305.DLL --  from fx-CG 10/20 emulator -- based on SH7724
Code: [Select]
0007E560   00 00 00 00 43 6D 6F 64  00 43 2D 73 70 65 63 69       Cmod C-speci
0007E570   66 69 63 61 74 69 6F 6E  20 6D 6F 64 75 6C 65 00   fication module
0007E580   44 44 43 4C 4B 52 30 00  45 78 74 65 72 6E 61 6C   DDCLKR0 External
0007E590   20 43 4C 4B 31 20 73 65  74 74 69 6E 67 00 44 44    CLK1 setting DD
0007E5A0   43 4C 4B 52 31 00 45 78  74 65 72 6E 61 6C 20 43   CLKR1 External C
0007E5B0   4C 4B 32 20 73 65 74 74  69 6E 67 00 44 44 43 4C   LK2 setting DDCL
0007E5C0   4B 52 32 00 45 78 74 65  72 6E 61 6C 20 43 4C 4B   KR2 External CLK
0007E5D0   33 20 73 65 74 74 69 6E  67 00 44 44 43 4B 5F 43   3 setting DDCK_C
0007E5E0   4E 54 52 00 45 78 74 65  72 6E 61 6C 20 63 6C 6F   NTR External clo
0007E5F0   63 6B 20 63 6F 6E 74 72  6F 6C 00 44 44 43 53 5F   ck control DDCS_
0007E600   43 4E 54 52 00 45 78 74  65 72 6E 61 6C 20 43 53   CNTR External CS
0007E610   20 63 6F 6E 74 72 6F 6C  00 48 49 5A 5F 43 4E 54    control HIZ_CNT
0007E620   52 00 49 6E 74 65 72 72  75 70 74 20 70 69 6E 20   R Interrupt pin
0007E630   6C 65 76 65 6C 20 63 6F  6E 74 72 6F 6C 00 46 41   level control FA
0007E640   53 43 52 00 42 43 44 20  43 61 6C 63 75 6C 61 74   SCR BCD Calculat
0007E650   69 6F 6E 20 63 6F 6E 74  72 6F 6C 00 46 41 53 53   ion control FASS
0007E660   52 41 00 42 43 44 20 43  61 6C 63 75 6C 61 74 69   RA BCD Calculati
0007E670   6F 6E 20 73 6F 75 72 63  65 20 41 00 46 41 53 53   on source A FASS
0007E680   52 42 00 42 43 44 20 43  61 6C 63 75 6C 61 74 69   RB BCD Calculati
0007E690   6F 6E 20 73 6F 75 72 63  65 20 42 00 46 41 53 44   on source B FASD
0007E6A0   52 00 42 43 44 20 43 61  6C 63 75 6C 61 74 69 6F   R BCD Calculatio
0007E6B0   6E 20 72 65 73 75 6C 74  00 52 54 53 54 52 30 00   n result RTSTR0
0007E6C0   52 54 43 20 43 6C 6F 63  6B 20 74 69 6D 65 72 20   RTC Clock timer
0007E6D0   30 20 73 74 61 72 74 00  52 54 43 52 30 00 52 54   0 start RTCR0 RT
0007E6E0   43 20 43 6C 6F 63 6B 20  74 69 6D 65 72 20 30 20   C Clock timer 0
0007E6F0   63 6F 6E 74 72 6F 6C 00  52 54 43 4F 52 30 00 52   control RTCOR0 R
0007E700   54 43 20 43 6C 6F 63 6B  20 74 69 6D 65 72 20 30   TC Clock timer 0
0007E710   20 63 6F 6E 73 74 61 6E  74 00 52 54 43 4E 54 30    constant RTCNT0
0007E720   00 52 54 43 20 43 6C 6F  63 6B 20 74 69 6D 65 72    RTC Clock timer
0007E730   20 30 20 63 6F 75 6E 74  65 72 00 52 54 53 54 52    0 counter RTSTR
0007E740   31 00 52 54 43 20 43 6C  6F 63 6B 20 74 69 6D 65   1 RTC Clock time
0007E750   72 20 31 20 73 74 61 72  74 00 52 54 43 52 31 00   r 1 start RTCR1
0007E760   52 54 43 20 43 6C 6F 63  6B 20 74 69 6D 65 72 20   RTC Clock timer
0007E770   31 20 63 6F 6E 74 72 6F  6C 00 52 54 43 4F 52 31   1 control RTCOR1
0007E780   00 52 54 43 20 43 6C 6F  63 6B 20 74 69 6D 65 72    RTC Clock timer
0007E790   20 31 20 63 6F 6E 73 74  61 6E 74 00 52 54 43 4E    1 constant RTCN
0007E7A0   54 31 00 52 54 43 20 43  6C 6F 63 6B 20 74 69 6D   T1 RTC Clock tim
0007E7B0   65 72 20 31 20 63 6F 75  6E 74 65 72 00 52 54 53   er 1 counter RTS
0007E7C0   54 52 32 00 52 54 43 20  43 6C 6F 63 6B 20 74 69   TR2 RTC Clock ti
0007E7D0   6D 65 72 20 32 20 73 74  61 72 74 00 52 54 43 52   mer 2 start RTCR
0007E7E0   32 00 52 54 43 20 43 6C  6F 63 6B 20 74 69 6D 65   2 RTC Clock time
0007E7F0   72 20 32 20 63 6F 6E 74  72 6F 6C 00 52 54 43 4F   r 2 control RTCO
0007E800   52 32 00 52 54 43 20 43  6C 6F 63 6B 20 74 69 6D   R2 RTC Clock tim
0007E810   65 72 20 32 20 63 6F 6E  73 74 61 6E 74 00 52 54   er 2 constant RT
0007E820   43 4E 54 32 00 52 54 43  20 43 6C 6F 63 6B 20 74   CNT2 RTC Clock t
0007E830   69 6D 65 72 20 32 20 63  6F 75 6E 74 65 72 00 52   imer 2 counter R
0007E840   54 53 54 52 33 00 52 54  43 20 43 6C 6F 63 6B 20   TSTR3 RTC Clock
0007E850   74 69 6D 65 72 20 33 20  73 74 61 72 74 00 52 54   timer 3 start RT
0007E860   43 52 33 00 52 54 43 20  43 6C 6F 63 6B 20 74 69   CR3 RTC Clock ti
0007E870   6D 65 72 20 33 20 63 6F  6E 74 72 6F 6C 00 52 54   mer 3 control RT
0007E880   43 4F 52 33 00 52 54 43  20 43 6C 6F 63 6B 20 74   COR3 RTC Clock t
0007E890   69 6D 65 72 20 33 20 63  6F 6E 73 74 61 6E 74 00   imer 3 constant
0007E8A0   52 54 43 4E 54 33 00 52  54 43 20 43 6C 6F 63 6B   RTCNT3 RTC Clock
0007E8B0   20 74 69 6D 65 72 20 33  20 63 6F 75 6E 74 65 72    timer 3 counter
0007E8C0   00 52 54 53 54 52 34 00  52 54 43 20 43 6C 6F 63    RTSTR4 RTC Cloc
0007E8D0   6B 20 74 69 6D 65 72 20  34 20 73 74 61 72 74 00   k timer 4 start
0007E8E0   52 54 43 52 34 00 52 54  43 20 43 6C 6F 63 6B 20   RTCR4 RTC Clock
0007E8F0   74 69 6D 65 72 20 34 20  63 6F 6E 74 72 6F 6C 00   timer 4 control
0007E900   52 54 43 4F 52 34 00 52  54 43 20 43 6C 6F 63 6B   RTCOR4 RTC Clock
0007E910   20 74 69 6D 65 72 20 34  20 63 6F 6E 73 74 61 6E    timer 4 constan
0007E920   74 00 52 54 43 4E 54 34  00 52 54 43 20 43 6C 6F   t RTCNT4 RTC Clo
0007E930   63 6B 20 74 69 6D 65 72  20 34 20 63 6F 75 6E 74   ck timer 4 count
0007E940   65 72 00 52 54 53 54 52  35 00 52 54 43 20 43 6C   er RTSTR5 RTC Cl
0007E950   6F 63 6B 20 74 69 6D 65  72 20 35 20 73 74 61 72   ock timer 5 star
0007E960   74 00 52 54 43 52 35 00  52 54 43 20 43 6C 6F 63   t RTCR5 RTC Cloc
0007E970   6B 20 74 69 6D 65 72 20  35 20 63 6F 6E 74 72 6F   k timer 5 contro
0007E980   6C 00 52 54 43 4F 52 35  00 52 54 43 20 43 6C 6F   l RTCOR5 RTC Clo
0007E990   63 6B 20 74 69 6D 65 72  20 35 20 63 6F 6E 73 74   ck timer 5 const
0007E9A0   61 6E 74 00 52 54 43 4E  54 35 00 52 54 43 20 43   ant RTCNT5 RTC C
0007E9B0   6C 6F 63 6B 20 74 69 6D  65 72 20 35 20 63 6F 75   lock timer 5 cou
0007E9C0   6E 74 65 72 00 00 00 00  80 09 08 10 88 09 08 10   nter    €   ˆ
Code: [Select]
0007FA40   43 6D 6F 64 32 41 00 43  2D 73 70 65 63 69 66 69   Cmod2A C-specifi
0007FA50   63 61 74 69 6F 6E 20 6D  6F 64 75 6C 65 20 32 41   cation module 2A
0007FA60   00 43 48 52 4D 43 54 52  4C 00 43 68 61 72 61 63    CHRMCTRL Charac
0007FA70   74 65 72 20 65 78 74 65  6E 73 69 6F 6E 20 6F 70   ter extension op
0007FA80   65 72 61 74 69 6F 6E 20  63 6F 6E 74 72 6F 6C 00   eration control
0007FA90   43 48 52 43 4F 4C 4F 52  00 43 68 61 72 61 63 74   CHRCOLOR Charact
0007FAA0   65 72 20 63 6F 6C 6F 72  20 73 70 65 63 69 66 69   er color specifi
0007FAB0   63 61 74 69 6F 6E 00 43  48 52 52 41 44 44 52 00   cation CHRRADDR
0007FAC0   43 68 61 72 61 63 74 65  72 20 64 61 74 61 20 72   Character data r
0007FAD0   65 61 64 20 73 74 61 72  74 20 61 64 64 72 65 73   ead start addres
0007FAE0   73 00 43 48 52 53 49 5A  45 00 43 68 61 72 61 63   s CHRSIZE Charac
0007FAF0   74 65 72 20 64 61 74 61  20 72 65 61 64 20 6C 65   ter data read le
0007FB00   6E 67 74 68 00 4D 53 4B  52 41 44 44 52 00 4D 61   ngth MSKRADDR Ma
0007FB10   73 6B 20 64 61 74 61 20  72 65 61 64 20 73 74 61   sk data read sta
0007FB20   72 74 20 61 64 64 72 65  73 73 00 56 52 4D 57 41   rt address VRMWA
0007FB30   44 44 52 00 56 52 41 4D  20 77 72 69 74 65 20 73   DDR VRAM write s
0007FB40   74 61 72 74 20 61 64 64  72 65 73 73 00 56 52 4D   tart address VRM
0007FB50   57 53 42 49 54 00 56 52  41 4D 20 77 72 69 74 65   WSBIT VRAM write
0007FB60   20 73 74 61 72 74 20 62  69 74 00 56 52 4D 41 52    start bit VRMAR
0007FB70   45 41 00 56 52 41 4D 20  61 72 65 61 00 44 45 53   EA VRAM area DES
0007FB80   57 41 44 44 52 00 44 65  73 74 69 6E 61 74 69 6F   WADDR Destinatio
0007FB90   6E 20 77 72 69 74 65 20  73 74 61 72 74 20 61 64   n write start ad
0007FBA0   64 72 65 73 73 00 44 45  53 41 52 45 41 00 44 65   dress DESAREA De
0007FBB0   73 74 69 6E 61 74 69 6F  6E 20 61 72 65 61 00 44   stination area D
0007FBC0   4D 41 4D 43 54 52 4C 00  44 4D 41 20 64 61 74 61   MAMCTRL DMA data
0007FBD0   20 74 72 61 6E 73 66 65  72 20 6F 70 65 72 61 74    transfer operat
0007FBE0   69 6F 6E 20 63 6F 6E 74  72 6F 6C 00 56 52 4D 52   ion control VRMR
0007FBF0   41 44 44 52 00 56 52 41  4D 20 64 61 74 61 20 72   ADDR VRAM data r
0007FC00   65 61 64 20 73 74 61 72  74 20 61 64 64 72 65 73   ead start addres
0007FC10   73 00 56 52 4D 52 53 49  5A 45 00 56 52 41 4D 20   s VRMRSIZE VRAM
0007FC20   64 61 74 61 20 72 65 61  64 20 6C 65 6E 67 74 68   data read length
0007FC30   00 44 44 57 50 4F 49 4E  54 31 00 44 2F 44 2D 52    DDWPOINT1 D/D-R
0007FC40   41 4D 20 77 72 69 74 65  20 73 74 61 72 74 20 70   AM write start p
0007FC50   6F 69 6E 74 65 72 20 31  00 44 44 57 50 4F 49 4E   ointer 1 DDWPOIN
0007FC60   54 32 00 44 2F 44 2D 52  41 4D 20 77 72 69 74 65   T2 D/D-RAM write
0007FC70   20 73 74 61 72 74 20 70  6F 69 6E 74 65 72 20 32    start pointer 2
0007FC80   00 44 44 57 50 4F 49 4E  54 33 00 44 2F 44 2D 52    DDWPOINT3 D/D-R
0007FC90   41 4D 20 77 72 69 74 65  20 73 74 61 72 74 20 70   AM write start p
0007FCA0   6F 69 6E 74 65 72 20 33  00 44 44 57 50 4F 49 4E   ointer 3 DDWPOIN
0007FCB0   54 34 00 44 2F 44 2D 52  41 4D 20 77 72 69 74 65   T4 D/D-RAM write
0007FCC0   20 73 74 61 72 74 20 70  6F 69 6E 74 65 72 20 34    start pointer 4
0007FCD0   00 44 44 57 53 49 5A 45  31 00 44 2F 44 2D 52 41    DDWSIZE1 D/D-RA
0007FCE0   4D 20 77 72 69 74 65 20  6C 65 6E 67 74 68 20 31   M write length 1
0007FCF0   00 44 44 57 53 49 5A 45  32 00 44 2F 44 2D 52 41    DDWSIZE2 D/D-RA
0007FD00   4D 20 77 72 69 74 65 20  6C 65 6E 67 74 68 20 32   M write length 2
0007FD10   00 44 44 57 53 49 5A 45  33 00 44 2F 44 2D 52 41    DDWSIZE3 D/D-RA
0007FD20   4D 20 77 72 69 74 65 20  6C 65 6E 67 74 68 20 33   M write length 3
0007FD30   00 44 44 57 53 49 5A 45  34 00 44 2F 44 2D 52 41    DDWSIZE4 D/D-RA
0007FD40   4D 20 77 72 69 74 65 20  6C 65 6E 67 74 68 20 34   M write length 4
0007FD50   00 44 44 41 52 45 41 31  00 44 2F 44 2D 52 41 4D    DDAREA1 D/D-RAM
0007FD60   20 61 72 65 61 20 31 00  44 44 41 52 45 41 32 00    area 1 DDAREA2
0007FD70   44 2F 44 2D 52 41 4D 20  61 72 65 61 20 32 00 44   D/D-RAM area 2 D
0007FD80   44 41 52 45 41 33 00 44  2F 44 2D 52 41 4D 20 61   DAREA3 D/D-RAM a
0007FD90   72 65 61 20 33 00 44 44  41 52 45 41 34 00 44 2F   rea 3 DDAREA4 D/
0007FDA0   44 2D 52 41 4D 20 61 72  65 61 20 34 00 4C 41 59   D-RAM area 4 LAY
0007FDB0   4D 43 54 52 4C 00 4C 61  79 65 72 20 6F 70 65 72   MCTRL Layer oper
0007FDC0   61 74 69 6F 6E 20 63 6F  6E 74 72 6F 6C 00 00 00   ation control
« Last Edit: March 16, 2013, 01:13:16 pm by cfxm »

Offline DJ Omnimaga

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Re: Casio Prizm documentation
« Reply #633 on: March 13, 2013, 01:06:45 am »
Interesting find Cfxm :)
In case you are wondering where I went, I left Omni back in 2015 to form CodeWalrus due to various reasons explained back then, but I stopped calc dev in 2016 and am now mostly active on the CW Discord server at https://discord.gg/cuZcfcF



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