ADC



ADC A,(HL)

Adds a to (hl) and the carry flag, stores result in a.
The zero flag is set if the result is zero, and the carry flag is set if the result is
greater than 255.

ADC A,A
ADC A,B
ADC A,C
ADC A,D
ADC A,E
ADC A,H
ADC A,L
ADC A,IXH
ADC A,IXL
ADC A,IYH
ADC A,IYL

Adds a to another register and the carry flag, stores result in a.

ADC A,(IX+[offset])
ADC A,(IY+[offset])

Adds a to (ix+[offset]) or (iy+[offset]) and the carry flag,
stores result in a.

ADC A,[number]

Adds a to [number] and the carry flag, stores result in a.

ADC HL,BC
ADC HL,DE
ADC HL,HL
ADC HL,SP

Adds hl to another register and the carry flag, stores result in hl.
The carry flag is set if the result is greater than 65535.

ADD



ADD A,(HL)

Adds a to (hl), stores result in a. The zero flag is set if the result is 0,
and the carry flag is set if the result is greater than 255.

ADD A,A
ADD A,B
ADD A,C
ADD A,D
ADD A,E
ADD A,H
ADD A,L
ADD A,IXH
ADD A,IXL
ADD A,IYH
ADD A,IYL

Adds a to another register, stores result in a.

ADD A,(IX+[offset])
ADD A,(IY+[offset])

Adds a to (ix+[offset]) or (iy+[offset]), stores result in a.

ADD A,[number]

Adds a to [number], stores result in a.

ADD HL,BC
ADD HL,DE
ADD HL,HL
ADD HL,SP

Adds hl to another register, stores result in hl. The carry flag is set if the
result is greater than 65535.

ADD IX,BC
ADD IX,DE
ADD IX,IX
ADD IX,SP

Adds ix to another register, stores result in ix.

ADD IY,BC
ADD IY,DE
ADD IY,IY
ADD IY,SP

Adds iy to another register, stores result in iy.

AND



AND (HL)

Performs a logical AND with a and (hl), stores result in a.
The zero flag is set if the result is zero, and the carry flag is cleared.

AND A
AND B
AND C
AND D
AND E
AND H
AND L
AND IXH
AND IXL
AND IYH
AND IYL

Performs a logical AND with a and another register, stores result in a.

AND (IX+[offset])
AND (IY+[offset])

Performs a logical AND with a and (ix+[offset]) or (iy+[offset]),
stores result in a.

AND [number]

Performs a logical AND with a and [number], stores result in a.

BIT



BIT [bit],(HL)

Tests [bit] in (hl), sets the zero flag if it's
set to 0 and clears the zero flag if it's set to 1.

BIT [bit],(IX+[offset])
BIT [bit],(IY+[offset])

Tests [bit] in (ix+[offset]) or (iy+[offset]).

BIT [bit],A
BIT [bit],B
BIT [bit],C
BIT [bit],D
BIT [bit],E
BIT [bit],H
BIT [bit],L

Tests [bit] in one of the registers.

CALL



CALL [address]

Calls a routine by pushing the current program counter address on the stack
and jumping to [address].

CALL C,[address]

Calls [address] if the carry flag is set.

CALL NC,[address]

Calls [address] if the carry flag is cleared.

CALL M,[address]

?

CALL Z,[address]

Calls [address] if the zero flag is set.

CALL NZ,[address]

Calls [address] if the zero flag is cleared.

CALL P,[address]
CALL PE,[address]
CALL PO,[address]

?

CCF/SCF



CCF

Clears the carry flag.

SCF

Sets the carry flag.

CP



CP (HL)

Compares a to (hl) by subtracting (hl) from a and throwing the result away,
but setting the flags anyways. The zero flag is set if the numbers are equal, and the carry flag is
set if (hl) is greater than a.

CP (IX+[offset])
CP (IY+[offset])

Compares a to (ix+[offset]) or (iy+[offset]).

CP A

Compares a to itself. Always sets the zero flag and clears the carry flag.

CP B
CP C
CP D
CP E
CP H
CP L
CP IXH
CP IXL
CP IYH
CP IYL

Compares a to another register.

CP [number]

Compares a to [number].

CPD

Compares a to (hl), decrements hl and bc.

CPDR

Compares a to (hl), decrements hl and bc,
repeats until the numbers are equal or bc is zero.

CPI

Compares a to (hl), increments hl and decrements bc.

CPIR

Compares a to (hl), increments hl and decrements bc,
repeats until the numbers are equal or bc is zero.


CPL/NEG



CPL

Sets a to the bitwise NOT (one's complement) of itself.

NEG

Sets a to the negative (two's complement) of itself.


DEC/DJNZ



DEC (HL)

Decrements (hl), sets the zero flag if the new value is zero.

DEC (IX+[offset])
DEC (IY+[offset])

Decrements (ix+[offset]) or (iy+[offset]).

DEC A
DEC B
DEC C
DEC D
DEC E
DEC H
DEC L
DEC IXH
DEC IXL
DEC IYH
DEC IYL
DEC BC
DEC DE
DEC HL
DEC IX
DEC IY

Decrements a register.

DEC SP

Decrements the stack pointer.

DJNZ [address]

Decrements b, if not zero jumps to [address]. Doesn't affect any flags.

EX/EXX



EX (SP),HL
EX (SP),IX
EX (SP),IY

Exchanges the top value on the stack with hl, ix, or iy.

EX AF,AF'

Exchanges the contents of af and af' (alternate af).

EX DE,HL

Exchanges the contents of de and hl.

EXX

Exchanges the contents of all the normal registers and alternate registers.
(af with af', bc with bc', de with de', etc.)

DI/EI/IM



DI

Disables interrupts.

EI

Enables interrupts.

IM 0

Switches to interrupt mode 0. This isn't at all useful and is never used on
the TI calculators - when an interrupt occurs, the Z80 takes an instruction
from the data bus and executes it immediately.

IM 1

Switches to interrupt mode 1. This is the normal interrupt mode - when an
interrupt occurs, the Z80 pushes the current program counter address on the
stack, disables interrupts, and jumps to $0038.

IM 2

Switches to interrupt mode 2. This mode is usually used for bypassing the
calculator's built-in interrupt handler - when an interrupt occurs, the Z80
pushes the current program counter address on the stack, disables interrupts,
then gets the high byte of an address from the i register and the low
byte from the data bus, retrieves a new address from that address in memory,
and jumps to the new address.

HALT

Puts the Z80 in a low-power mode and waits for an interrupt.


IN/IND/INI/INDR/INIR



IN A,(C)
IN B,(C)
IN C,(C)
IN D,(C)
IN E,(C)
IN F,(C)
IN H,(C)
IN L,(C)

Reads a byte from the port number held in c and stores it in a register.

IN A,([number])

Reads a byte from port [number] and stores it in a.

INI

Gets a byte from the port number held in c, stores it at (hl)
and increments hl, decrements b.

INIR

Gets a byte from the port number held in c, stores it at (hl)
and increments hl, decrements b, repeats until b is zero.

IND

Gets a byte from the port number held in c, stores it at (hl)
and decrements hl and b.

INDR

Gets a byte from the port number held in c, stores it at (hl)
and decrements hl and b, repeats until b is zero.

INC



INC A
INC B
INC BC
INC C
INC D
INC DE
INC E
INC H
INC HL
INC IX
INC IXH
INC IXL
INC IY
INC IYH
INC IYL
INC L
INC SP

Increments a register, sets the zero flag if the value overflows to 0.

INC (HL)

Increments (hl).

INC (IX+[offset])
INC (IY+[offset])

Increments (ix+[offset]) or (iy+[offset]).
In this case, the zero flag is not affected.

JP



JP [address]

Jumps to [address].

JP (HL)
JP (IX)
JP (IY)

Jumps to the address held in hl, ix, or iy.

JP Z,[address]

Jumps to [address] if the zero flag is set.

JP NZ,[address]

Jumps to [address] if the zero flag is cleared.

JP C,[address]

Jumps to [address] if the carry flag is set.

JP NC,[address]

Jumps to [address] if the carry flag is cleared.

JP M,[address]

?

JP P,[address]

?

JP PE,[address]

?

JP PO,[address]

?

JR



JR [address]

Jumps to [address], which must be less than 128 bytes
from the current location in the program.

JR Z,[address]

Jumps to [address] if the zero flag is set.

JR NZ,[address]

Jumps to [address] if the zero flag is cleared.

JR C,[address]

Jumps to [address] if the carry flag is set.

JR NC,[address]

Jumps to [address] if the carry flag is cleared.

LD



LD (HL),A
LD (HL),B
LD (HL),C
LD (HL),D
LD (HL),E
LD (HL),H
LD (HL),L
LD (BC),A
LD (DE),A

Loads (hl), (bc), or (de) with the contents of a register.

LD (IX+[offset]),[number]
LD (IY+[offset]),[number]

Loads (ix+[offset]) or (iy+[offset]) with [number].

LD (IX+[offset]),A
LD (IX+[offset]),B
LD (IX+[offset]),C
LD (IX+[offset]),D
LD (IX+[offset]),E
LD (IX+[offset]),H
LD (IX+[offset]),L
LD (IY+[offset]),A
LD (IY+[offset]),B
LD (IY+[offset]),C
LD (IY+[offset]),D
LD (IY+[offset]),E
LD (IY+[offset]),H
LD (IY+[offset]),L

Loads (ix+[offset]) or (iy+[offset]) with the contents of a register.

LD ([address]),A

Loads ([address]) with a.

LD ([address]),BC
LD ([address]),DE
LD ([address]),HL
LD ([address]),IX
LD ([address]),IY
LD ([address]),SP

Loads ([address]) with the contents of a register, with the least-significant byte first.

LD A,(HL)
LD B,(HL)
LD C,(HL)
LD D,(HL)
LD E,(HL)
LD H,(HL)
LD L,(HL)
LD A,(BC)
LD A,(DE)

Loads a register with (hl), (bc), or (de).

LD A,(IX+[offset])
LD A,(IY+[offset])
LD B,(IX+[offset])
LD B,(IY+[offset])
LD C,(IX+[offset])
LD C,(IY+[offset])
LD D,(IX+[offset])
LD D,(IY+[offset])
LD E,(IX+[offset])
LD E,(IY+[offset])
LD H,(IX+[offset])
LD H,(IY+[offset])
LD L,(IX+[offset])
LD L,(IY+[offset])

Loads a register with (ix+[offset]) or (iy+[offset]).

LD A,([address])

Loads a with ([address]).

LD BC,([address])
LD DE,([address])
LD HL,([address])
LD IX,([address])
LD IY,([address])
LD SP,([address])

Loads a register with ([address]), with the least-significant byte coming first in memory.

LD A,[number]
LD B,[number]
LD C,[number]
LD D,[number]
LD E,[number]
LD H,[number]
LD L,[number]
LD SP,[number]
LD BC,[number]
LD DE,[number]
LD HL,[number]
LD IX,[number]
LD IY,[number]
LD IXH,[number]
LD IXL,[number]
LD IYH,[number]
LD IYL,[number]

Loads a register with [number].

LD A,A
LD A,B
LD A,C
LD A,D
LD A,E
LD A,H
LD A,L
LD A,I
LD A,IXH
LD A,IXL
LD A,IYH
LD A,IYL
LD A,R
LD B,A
LD B,B
LD B,C
LD B,D
LD B,E
LD B,H
LD B,IXH
LD B,IXL
LD B,IYH
LD B,IYL
LD B,L
LD C,A
LD C,B
LD C,C
LD C,D
LD C,E
LD C,H
LD C,IXH
LD C,IXL
LD C,IYH
LD C,IYL
LD C,L
LD D,A
LD D,B
LD D,C
LD D,D
LD D,E
LD D,H
LD D,IXH
LD D,IXL
LD D,IYH
LD D,IYL
LD D,L
LD E,A
LD E,B
LD E,C
LD E,D
LD E,E
LD E,H
LD E,IXH
LD E,IXL
LD E,IYH
LD E,IYL
LD E,L
LD H,A
LD H,B
LD H,C
LD H,D
LD H,E
LD H,H
LD H,L
LD I,A
LD IXH,A
LD IXH,B
LD IXH,C
LD IXH,D
LD IXH,E
LD IXH,IXH
LD IXH,IXL
LD IXL,A
LD IXL,B
LD IXL,C
LD IXL,D
LD IXL,E
LD IXL,IXH
LD IXL,IXL
LD IYH,A
LD IYH,B
LD IYH,C
LD IYH,D
LD IYH,E
LD IYH,IYH
LD IYH,IYL
LD IYL,A
LD IYL,B
LD IYL,C
LD IYL,D
LD IYL,E
LD IYL,IYH
LD IYL,IYL
LD L,A
LD L,B
LD L,C
LD L,D
LD L,E
LD L,H
LD L,L
LD R,A
LD SP,HL
LD SP,IX
LD SP,IY

Loads a register with the contents of another register.

LDI

Copies (hl) to (de), increments hl and de, decrements bc.

LDIR

Copies (hl) to (de), increments hl and de, decrements bc
and repeats until bc is zero.

LDD

Copies (hl) to (de), decrements hl, de, and bc.

LDDR

Copies (hl) to (de), decrements hl, de, and bc,
repeats until bc is zero.


NOP



NOP

Does nothing for one cycle, useful for very short delays in
keypress routines and similar code.


OR



OR (HL)

Performs a logical OR with a and (hl), stores the result in a.

OR (IX+[offset])
OR (IY+[offset])

Performs a logical OR with a and (ix+[offset]) or (iy+[offset]),
stores the result in a.

OR A
OR B
OR C
OR D
OR E
OR H
OR IXH
OR IXL
OR IYH
OR IYL
OR L

Performs a logical OR with a and another register, stores the result in a.

OR [number]

Performs a logical OR with a and [number], stores the result in a.


OUT/OUTI/OTIR/OUTD/OTDR



OUT (C),A
OUT (C),B
OUT (C),C
OUT (C),D
OUT (C),E
OUT (C),F
OUT (C),H
OUT (C),L

Outputs the contents of a register on the port number held in c.

OUT (C),0

?

OUT ([port]),A

Outputs the contents of a on [port].

OUTI

Outputs (hl) on the port number held in c, decrements b and increments hl.

OTIR

Outputs (hl) on the port number held in c, decrements b and increments hl,
repeats until b is zero.

OUTD

Outputs (hl) on the port number held in c, decrements b and hl.

OTDR

Outputs (hl) on the port number held in c, decrements b and hl,
repeats until b is zero.


POP



POP AF
POP BC
POP DE
POP HL
POP IX
POP IY

Pops a word off the top of the stack and puts it into a register pair.


PUSH



PUSH AF
PUSH BC
PUSH DE
PUSH HL
PUSH IX
PUSH IY

Pushes the contents of a register pair onto the top of the stack.


RES



RES [bit],(HL)

Clears [bit] in (hl).

RES [bit],(IX+[offset])
RES [bit],(IY+[offset])

Clears [bit] in (ix+[offset]) or (iy+[offset]).

RES [bit],A
RES [bit],B
RES [bit],C
RES [bit],D
RES [bit],E
RES [bit],H
RES [bit],L

Clears [bit] in a register.

RES A,[bit],(IX+[offset])
RES A,[bit],(IY+[offset])
RES B,[bit],(IX+[offset])
RES B,[bit],(IY+[offset])
RES C,[bit],(IX+[offset])
RES C,[bit],(IY+[offset])
RES D,[bit],(IX+[offset])
RES D,[bit],(IY+[offset])
RES E,[bit],(IX+[offset])
RES E,[bit],(IY+[offset])
RES H,[bit],(IX+[offset])
RES H,[bit],(IY+[offset])
RES L,[bit],(IX+[offset])
RES L,[bit],(IY+[offset])

Clears [bit] in a register and (ix+[offset]) or (iy+[offset]).


RET/RETI/RETN



RET

Returns from a routine by popping an address off the top of the stack and
jumping to it.

RET C

Returns if the carry flag is set.

RET NC

Returns if the carry flag is cleared.

RET Z

Returns if the zero flag is set.

RET NZ

Returns if the zero flag is cleared.

RET M

?

RET P

?

RET PE

?

RET PO

?

RETI

Returns from an interrupt service routine. This is just like a normal ret
instruction, except it enables interrupts at the same time.

RETN

Returns from an interrupt service routine for a non-maskable interrupt. Since
non-maskable interrupts aren't used on the TI calculators (as far as I know),
this isn't very useful.


RL



RL (HL)

Rotates (hl) left, taking the rightmost bit from the carry flag and moving the leftmost bit
to the carry flag.

RL (IX+[offset])
RL (IY+[offset])

Rotates (ix+[offset]) or (iy+[offset]) left.

RL A
RL B
RL C
RL D
RL E
RL H
RL L

Rotates a register left.

RLA

Rotates a left.

RL A,(IX+[offset])
RL A,(IY+[offset])
RL B,(IX+[offset])
RL B,(IY+[offset])
RL C,(IX+[offset])
RL C,(IY+[offset])
RL D,(IX+[offset])
RL D,(IY+[offset])
RL E,(IX+[offset])
RL E,(IY+[offset])
RL H,(IX+[offset])
RL H,(IY+[offset])
RL L,(IX+[offset])
RL L,(IY+[offset])

Rotates a register and (ix+[offset]) or (iy+[offset]) left.


RLC



RLC (HL)

Rotates (hl) left, moving the leftmost bit into the rightmost bit.

RLC (IX+[offset])
RLC (IY+[offset])

Rotates (ix+[offset]) or (iy+[offset]) left.

RLC A
RLC B
RLC C
RLC D
RLC E
RLC H
RLC L

Rotates a register left.

RLCA

Rotates a left.

RLC A,(IX+[offset])
RLC A,(IY+[offset])
RLC B,(IX+[offset])
RLC B,(IY+[offset])
RLC C,(IX+[offset])
RLC C,(IY+[offset])
RLC D,(IX+[offset])
RLC D,(IY+[offset])
RLC E,(IX+[offset])
RLC E,(IY+[offset])
RLC H,(IX+[offset])
RLC H,(IY+[offset])
RLC L,(IX+[offset])
RLC L,(IY+[offset])

Rotates a register and (ix+[offset]) or (iy+[offset]) left.

RLD

?


RR



RR (HL)

Rotates (hl) right, taking the leftmost bit from the carry flag and moving the rightmost bit
to the carry flag.

RR (IX+[offset])
RR (IY+[offset])

Rotates (ix+[offset]) or (iy+[offset]) right.

RR A
RR B
RR C
RR D
RR E
RR H
RR L

Rotates a register right.

RR A,(IX+[offset])
RR A,(IY+[offset])
RR B,(IX+[offset])
RR B,(IY+[offset])
RR C,(IX+[offset])
RR C,(IY+[offset])
RR D,(IX+[offset])
RR D,(IY+[offset])
RR E,(IX+[offset])
RR E,(IY+[offset])
RR H,(IX+[offset])
RR H,(IY+[offset])
RR L,(IX+[offset])
RR L,(IY+[offset])

Rotates a register and (ix+[offset]) or (iy+[offset]) right.

RRA

Rotates a right.


RRC



RRC (HL)

Rotates (hl) right, moving the rightmost bit into the leftmost bit.

RRC (IX+[offset])
RRC (IY+[offset])

Rotates (ix+[offset]) or (iy+[offset]) right.

RRC A
RRC B
RRC C
RRC D
RRC E
RRC H
RRC L

Rotates a register right.

RRCA

Rotates a right.

RRC A,(IX+[offset])
RRC A,(IY+[offset])
RRC B,(IX+[offset])
RRC B,(IY+[offset])
RRC C,(IX+[offset])
RRC C,(IY+[offset])
RRC D,(IX+[offset])
RRC D,(IY+[offset])
RRC E,(IX+[offset])
RRC E,(IY+[offset])
RRC H,(IX+[offset])
RRC H,(IY+[offset])
RRC L,(IX+[offset])
RRC L,(IY+[offset])

Rotates a register and (ix+[offset]) or (iy+[offset]) right.

RRD

?


RST



RST 00h
RST 08h
RST 10h
RST 18h
RST 20h
RST 28h
RST 30h
RST 38h

Calls 0000h, 0008h, 0010h, 0018h... The advantage of using these rather than
"call 0000h", "call 0008h", etc. is that they're smaller.


SBC



SBC A,(HL)

Subtracts (hl) plus the carry bit from a, stores the result in a.

SBC A,(IX+[offset])
SBC A,(IY+[offset])

Subtracts (ix+[offset]) or (ix+[offset])
plus the carry bit from a, stores the result in a.

SBC A,A
SBC A,B
SBC A,C
SBC A,D
SBC A,E
SBC A,H
SBC A,IXH
SBC A,IXL
SBC A,IYH
SBC A,IYL
SBC A,L

Subtracts the contents of a register plus the carry bit from a, stores the
result in a.

SBC HL,BC
SBC HL,DE
SBC HL,HL
SBC HL,SP

Subtracts the contents of a register pair plus the carry bit from hl, stores
the result in hl.

SBC A,[number]

Subtracts [number] plus the carry bit from a, stores the
result in a.


SET



SET [bit],(HL)

Sets [bit] in (hl).

SET [bit],(IX+[offset])
SET [bit],(IY+[offset])

Sets [bit] in (ix+[offset]) or (iy+[offset]).

SET [bit],A
SET [bit],B
SET [bit],C
SET [bit],D
SET [bit],E
SET [bit],H
SET [bit],L

Sets [bit] in a register.

SET A,[bit],(IY+[offset])
SET B,[bit],(IY+[offset])
SET C,[bit],(IY+[offset])
SET D,[bit],(IY+[offset])
SET E,[bit],(IY+[offset])
SET H,[bit],(IY+[offset])
SET L,[bit],(IY+[offset])
SET A,[bit],(IX+[offset])
SET B,[bit],(IX+[offset])
SET C,[bit],(IX+[offset])
SET D,[bit],(IX+[offset])
SET E,[bit],(IX+[offset])
SET H,[bit],(IX+[offset])
SET L,[bit],(IX+[offset])

Sets [bit] in register and (ix+[offset]) or (iy+[offset]).

SLA



SLA (HL)

Shifts (hl) left, moving the leftmost bit into the carry flag and clearing the rightmost bit.

SLA (IX+[offset])
SLA (IY+[offset])

Shifts (ix+[offset]) or (iy+[offset]) left.

SLA A
SLA B
SLA C
SLA D
SLA E
SLA H
SLA L

Shifts a register left.

SLA A,(IX+[offset])
SLA A,(IY+[offset])
SLA B,(IX+[offset])
SLA B,(IY+[offset])
SLA C,(IX+[offset])
SLA C,(IY+[offset])
SLA D,(IX+[offset])
SLA D,(IY+[offset])
SLA E,(IX+[offset])
SLA E,(IY+[offset])
SLA H,(IX+[offset])
SLA H,(IY+[offset])
SLA L,(IX+[offset])
SLA L,(IY+[offset])

Shifts a register and (ix+[offset]) or (iy+[offset]) left.

SLL



SLL (HL)

Shifts (hl) left and sets the rightmost bit.

SLL (IX+[offset])
SLL (IY+[offset])

Shifts (ix+[offset]) or (iy+[offset]) left.

SLL A
SLL B
SLL C
SLL D
SLL E
SLL H
SLL L

Shifts a register left.

SLL A,(IX+[offset])
SLL A,(IY+[offset])
SLL B,(IX+[offset])
SLL B,(IY+[offset])
SLL C,(IX+[offset])
SLL C,(IY+[offset])
SLL D,(IX+[offset])
SLL D,(IY+[offset])
SLL E,(IX+[offset])
SLL E,(IY+[offset])
SLL H,(IX+[offset])
SLL H,(IY+[offset])
SLL L,(IX+[offset])
SLL L,(IY+[offset])

Shifts a register and (ix+[offset]) or (iy+[offset]) left.


SRA



SRA (HL)

Shifts (hl) right, moving the rightmost bit into the carry flag and not touching the leftmost bit.

SRA (IX+[offset])
SRA (IY+[offset])

Shifts (ix+[offset]) or (iy+[offset]) right.

SRA A
SRA B
SRA C
SRA D
SRA E
SRA H
SRA L

Shifts a register right.

SRA A,(IX+[offset])
SRA A,(IY+[offset])
SRA B,(IX+[offset])
SRA B,(IY+[offset])
SRA C,(IX+[offset])
SRA C,(IY+[offset])
SRA D,(IX+[offset])
SRA D,(IY+[offset])
SRA E,(IX+[offset])
SRA E,(IY+[offset])
SRA H,(IX+[offset])
SRA H,(IY+[offset])
SRA L,(IX+[offset])
SRA L,(IY+[offset])

Shifts a register and (ix+[offset]) or (iy+[offset]) right.

SRL



SRL (HL)

Shifts (hl) right, moving the rightmost bit into the carry flag and clearing the leftmost bit.

SRL (IX+[offset])
SRL (IY+[offset])

Shifts (ix+[offset]) or (iy+[offset]) right.

SRL A
SRL B
SRL C
SRL D
SRL E
SRL H
SRL L

Shifts a register right.

SRL A,(IX+[offset])
SRL A,(IY+[offset])
SRL B,(IX+[offset])
SRL B,(IY+[offset])
SRL C,(IX+[offset])
SRL C,(IY+[offset])
SRL D,(IX+[offset])
SRL D,(IY+[offset])
SRL E,(IX+[offset])
SRL E,(IY+[offset])
SRL H,(IX+[offset])
SRL H,(IY+[offset])
SRL L,(IX+[offset])
SRL L,(IY+[offset])

Shifts a register and (ix+[offset]) or (iy+[offset]) right.


SUB



SUB (HL)

Subtracts (hl) from a, stores the result in a.

SUB (IX+[offset])
SUB (IY+[offset])

Subtracts (ix+[offset]) or (iy+[offset]) from a,
stores the result in a.

SUB A
SUB B
SUB C
SUB D
SUB E
SUB H
SUB IXH
SUB IXL
SUB IYH
SUB IYL
SUB L

Subtracts a register from a, stores the result in a.

SUB [number]

Subtracts [number] from a, stores the result in a.

XOR (HL)

Performs a logical XOR with a and (hl), stores the result in a.

XOR (IX+[offset])
XOR (IY+[offset])

Performs a logical XOR with a and (ix+[offset]) or (iy+[offset]),
stores the result in a.

XOR A
XOR B
XOR C
XOR D
XOR E
XOR H
XOR IXH
XOR IXL
XOR IYH
XOR IYL
XOR L

Performs a logical XOR with a and another register, stores the result in a.

XOR [number]

Performs a logical XOR with a and [number], stores the result in a.