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Play it safe with the Ti-83+/Ti-84+ Screen

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the_mad_joob:
Hello there.

Sorry for the necro, but it's a sticky thread, and random people ending up here might wanna know about this.
Apparently, the method of checking bit 7 of port $10 isn't reliable on all hardwares anymore =[
That means, only the following methods remain :

# busy state check : all models except TI-83+ non-SE - CPU speeds 1|2|3 only
Check bit 1 of port $02 (0=busy|1=ready).
Note that though it doesn't mean the LCD is actually ready, the bit will always be set on the TI-83+ non-SE, or if using CPU speed 0.
The busy state duration is defined through port $2F.

# automatic delay : all models except TI-83+ non-SE
The delay duration is defined through ports $29|$2A|$2B|$2C (CPU speeds 0|1|2|3 respectively).

# manual delay : all models
Actually the only remaining method for TI-83+ non-SE.

Xeda112358:
Oh, thank you for adding this update! It's annoying that these new calcs don't work the same .__.

the_mad_joob:

--- Quote from: Xeda112358 on August 27, 2020, 06:33:39 am ---Oh, thank you for adding this update! It's annoying that these new calcs don't work the same .__.

--- End quote ---
Definitely.
TI probably invested in new LCDs or controllers, cheaper than the ones we had back in the days.
However, no matter which new hardware TI decides to implement, it can't be slower than the delays used by the OS, otherwise they would need to update it.
Following such logic, i inspected the latest TI-OS for each model (TI-83+[SE] : 1.19 | TI-84+[SE] : 2.55).
Basically, the system always uses at least these numbers (total clock cycles between instructions).
Note that these amounts are only valid while having ports $29,$2A,$2E,$2F holding default values.
There you go :

TI-83+ : 73
TI-83+SE @ CPU speed 0 : 73
TI-84+ @ CPU speed 0 : 139
TI-84+SE @ CPU speed 0 : 139
TI-83+SE @ CPU speed 1 : 215
TI-84+ @ CPU speed 1 : 339
TI-84+SE @ CPU speed 1 : 339

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