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DrDnar:
If you request an account, be sure to ping me on IRC, or might not get approved for some time, because I don't check the queue everyday.


--- Quote from: the_mad_joob on May 11, 2014, 04:45:28 pm ---About that : http://wikiti.brandonw.net/index.php?title=83Plus:Ports:01
In the example, a "xor" must be used, not an "and".

--- End quote ---
No, the example is correct. Reset for a bit means that the key is held, the following CALL instruction tests for Z, not NZ. If you use XOR, you have to reverse the test.


--- Quote from: the_mad_joob on May 11, 2014, 04:45:28 pm ---Also, a little paragraph about delays between writing & reading could be necessary, don't you think ?
For what we had tested, maximum cycles was 6 in cpu speed 0, and 29 in any other (about a dozen models tested).
The cse has longer delays, but we were only able to test one calc.

--- End quote ---
The TI-84+CSE uses the same ASIC (which handles the keyboard) as older TI-84+/SEs with 128 K RAM, so anything true of the TI-84+CSE ASIC is true of the older TI-84+/SE ASIC. I wouldn't be surprised if, on average, the delays required are lower on the TA2 ASIC, but you should still have some.

the_mad_joob:
Hmm... there's something i don't get, then.
If left is pressed, (1) will return $FD.
$FD and $FD = $FD, right ?
So, why checking if if the result is zero before calling ?
Can somebody tell me where i missunderstand it ?

And about the CSE delays, yes, i remember you were surprised when my code returned those results.
Maybe i f***ed up somewhere in it...

DrDnar:

--- Quote from: the_mad_joob on May 11, 2014, 06:28:04 pm ---$FD and $FD = $FD, right ?

--- End quote ---
Ah, you're right. It should say ~0FDh; that is, it should be ANDing with the complement of FD

the_mad_joob:
Actually, that should work with xor $FD.
Of course, that is only the case when only LEFT is pressed in that group...

/e : Thx for the editing, but btw, no calculator returned more than 6 cycles in cpu mode 0. All results there : http://www.omnimaga.org/asm-language/8x%28se%29-testers-needed/?PHPSESSID=4g7m837h7uo8jgcgmfpdcn1592

the_mad_joob:
Allright, since i was curious about it, i did some tests, but this time, resetting the port first.
When you do that, i can confirm that no delay is needed bewteen sending the group and reading the key.
However, a delay is now needed between resetting the port and sending the group.

A bit more visual explanation :
LD A,$FF
OUT (1),A < resetting the port
... < that is where i mesured how many cycles are needed before writing to the port again (likely to include an instruction to actually load the group to be monitored in A)
OUT (1),A < sending the group
(no delay needed here)
IN (1),A < reading the keys

I only tested my 84+se for now, but it is a good reference (had the longest possible delays in my previous tests).
That is what i got :
cpu speed 0 > 4 cycles needed (maybe less, but that is the minimum cycles you need to load your group in A anyway)
cpu speed 1,2,3 > 17 cycles needed

That is interesting, cause it could imply that writing to port 1 is faster than reading from it.

When i have time, i'll check if the delays are similar when using the C register for input/output...

EDIT :

When using the C register for input/output (as expected) :
cpu speed 0 > 4 cycles
cpu speed 1,2,3 > 16 cycles (one less than on the previous test, but that is probably because in/out operations take 1 more cycle)

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