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Xeda112358:
Speaking of the key port...
I don't know if anybody else does this, but in some high-speed programs that only use 1 or 2 groups, I disable interrupts, set the key group(s) I need, and I never have to write to the port again (just read). So for example, I made a Snake game that only used the arrows and [2nd], [mode], and [del], so I wrote $BE to the port. At the beginning of the game loop, I just need to do in a,(1) with no worry about delays to read the key press. So yeah, in some of my games, pressing things like F2 to F5 will also act as arrow presses.

Otherwise, if I need _GetK and the program needs to be small and can use interrupts, turn on interrupts and spend only 13 cycles to either read 8445h or 843Fh (whichever is needed) for the same effect.

Streetwalrus:
Oh wow that's what Soru was talking about the other day. O.O Nice trick.

Sorunome:

--- Quote from: Streetwalrus on May 13, 2014, 10:53:35 am ---Oh wow that's what Soru was talking about the other day. O.O Nice trick.

--- End quote ---
Hehe, I got the trick from Iambian and geekboy :P

the_mad_joob:
Yes xedy, reading multiple groups at the same time should be done, when possible =]

I'm very curious about something.
Like i said earlier, we basically have these 2 behaviours :

write
delay
read

or

reset
delay
write
read

The question is, why doing a reset removes the delay needed bewteen a write & a read ?
Hardware-speaking, i have no ideas how the keyboard really works, but i have a theory that could explain that.
What if :

Case 1 : The writing causes one or more group(s) to be disabled (one or more bit(s) in the group map changes from 0 to 1). > slow operation for the keybord, delay required before reading
That is the case when you switch from one group to another, for example.

Case 2 : All other cases (enabling groups or not modifying them) > very fast operation, no delay
That is the case when you write anything after having performed a reset, but also when you enable some more groups without disabling the previous ones.

I will try to verify that asap...

#####

EDIT 1 :

Ok, just tested it, and it doesn't work like that.
However, i found something strange.
Here is the code i used :

--- Code: ---    di

    ld a,1
    out ($20),a ; 15Mhz

    ld a,00000010b
    out (1),a ; enabling all groups except the one including [CLEAR]

    ld b,0
loop1
    djnz loop1

loop2

    ld a,11111101b
    out (1),a ; enabling group including [CLEAR]

    in a,(1)
    cp 10111111b ; checking if [CLEAR] being pressed
    jr nz,loop2
--- End code ---
As you can see, there is no delay before i read port 1.
Guess what ? PC actually exits the loop instantly when i press [CLEAR].
Any idea why ?

#####

EDIT 2 :
found out : loop2 starts, OUT done, IN skipped, jump, OUT skipped, IN done, exit
Not what i wanted to find, but anyway, it seems a delay is also needed between reading & writing...

#####

EDIT 3 :
Did some more tests.
It seems my initial theory was half-right.
I decided to create a dedicated topic about it.

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