How aboot teh "Nulator"? "Nspire Emulator"?

Or eNulator. It sounds almost the same except the m is replaced with an n.

Yeah, I probably should have given this thing a better name by now. I'm not too creative with names.
eNulator is nice, Nulator doesn't suggest the right pronounciation (without context, I would probably pronounce it null-a-tor or noo-later).

A while ago I came up with the name "TraNspire" - based on the way that I get decent emulation speed by translating ARM instructions into sequences of x86 instructions to emulate them.

There's no way to get documents out of nspire_emu; it's meant for testing and debugging asm/C programs, not for doing things the computer software does.

Anyway, I managed to dump the XML of the documents, remove the offending tag (it was just the cursor location, nothing important), zip them back up, and re-save on my TI-Nspire with OS 2.0.1 (in order to encrypt them - 3.0 doesn't allow unencrypted documents any more). Here you go.

Thanks for the offer, but there isn't anything I could do with a CAS+; I don't know of any way to run code on it.
Regarding the other calc, I am not a hardware guy; I can't fix a broken ribbon cable (and I already have a TI-Nspire anyway).

critor: Does your CX still have OS 3.0.1? I found a software exploit that might work.

List of all the high registers I could find that have special meaning to the emulator:
8-9: Stack pointer. Emulator masks off bits 0 and 7 when modified. References memory from 080 to 0FF
10-11: Bit 1: Enable ON key interrupt
Bit 2: Enable timer 1
Bit 3: Enable timer 2
Bit 4: Enable key press interrupt
Bit 5: Enable DMA complete interrupt
12-13: Bits 0-5: Select keypad rows
16-17: Bits 0-7: Bit set when key pressed
22: Bit 1: Set to start LCD update
23: Bit 0: Set to enable DRam bank/address auto-increment or decrement on access to 30-31
Bit 1: If set, DRam bank/address auto-decrements, otherwise auto-increments
24: Bit 0: Allow access to DRam banks 0-D
Bit 1: Allow access to DRam banks E-F
27: DRam bank
28-29: DRam address
30-31: DRam data. Access as a pair to read or write a byte
32-33: Bits 0-7: Key press interrupt column mask
40-41: Bit 0: ON key interrupt active
Bit 1: Timer 1 interrupt active
Bit 2: Timer 2 interrupt active
Bit 3: Key pressed interrupt active
Bit 4: DMA interrupt active
Bit 5: LCD interrupt active
42: Bits 0-1: Timer 1 interval
00 = 350000 TStates
01 = 350000 TStates
02 = 350000 TStates
03 = 350000 TStates (...yes, they're all the same)
Bit 2: Timer 1 interrupt enable
43: Bits 0-1: Timer 2 interval
00 = 6000 TStates
01 = 6000 TStates
02 = 6000 TStates
03 = 6000 TStates (...ditto)
Bit 2: Timer 2 interrupt enable
44: Bit 0: Set to enable timers
47: Bit 0: ON key pressed
Bit 3: Enable interrupt on ON key
48-50: DRam DMA byte count (000-7FF)
51: DRam DMA source bank
52-53: DRam DMA source address
56: DRam DMA bit shift count (0-7)
58: Bit 0: Set to start DMA; cleared when done
Bit 3: Interrupt when complete
59: DRam DMA destination bank
60-61: DRam DMA destination address


I went through the emulator's ProcessorCoreT4xFunctions class to make a quick list of what each instruction does; hopefully this will help in understanding the instructions that weren't mentioned in the document.

opcode  fields           cycles flags description
 0 0000 1111114433---222 1 -- nop (f3=0), halt (f3=2)
   0100                 invalid
   0200                 2 -- PC = PC + 1 + reg[f2]
   0300                 3 -- pop PC
 1 0400 1111114433332222 2 -- M = low byte of ROM[reg7:reg6:reg5:reg4]
   0500                 2 -- M = high byte of ROM[reg7:reg6:reg5:reg4]
   0600                 1 -- M = f2, L = L + f3
   0700                 1 -- M = f3:f2
 2 0800 11111144----2222 2 ZC add M, f2
   0900                 invalid
   0A00                 2 ZC sub M, f2
   0B00                 invalid
 3 0C00 11111144----2222 2 Z- and M, f2
   0D00                 2 Z- or  M, f2
   0E00                 2 Z- xor M, f2
   0F00                 1 ZC cmp M, f2
 4 1000 111111---------- invalid
 5 1400 1111114433332222 2 -- M = WRam[f3:f2]
   1500                 invalid
   1600                 4 -- swap M and WRam[f3:f2]
   1700                 invalid
 6 1800 111111443333---- 3 ZC block add WRam[f3:L] into WRam[H:L]: loops for A nybbles (0 = 16), L auto-increments
   1900                 3 ZC block BCD add
   1A00                 3 ZC block subtract
   1B00                 3 ZC block BCD subtract
 7 1C00 1111114433332222 2 -- block copy to WRam[H:(L+f2)] from WRam[f3:L]
   1D00                 2 -- block copy to WRam[H:(L+f2)] from WRam[f3:L] with decrementing L
   1E00                 4 -- block swap WRam[H:L] and WRam[f3:L]
   1F00                 2 ZC block compare WRam[H:L] to WRam[f3:L]
 8 2000 111111444-----22 1 -C load M and shift right (count is offset by 1)
 9 2400 111111444-----22 1 -C load M and shift left (count is offset by 1)
10 2800 111111333333---- 1 -- push regpair[f3]
11 2C00 111111333333---- 1 -- pop regpair[f3]
12 3000 111111444333--22 1 -C shift right (count is offset by 1)
13 3400 111111444333--22 1 -C shift left (count is offset by 1)
14 3800 111111333333---- 1 -- reg[f3] = M
15 3C00 111111333333---- 1 -- M = reg[f3]
16 4000 1111114443332222 1 ZC add reg[f4], reg[f3], f2
17 4400 111111444333-222 1 ZC add reg[f4], reg[f3], reg[f2]
18 4800 1111114443332222 1 ZC sub reg[f4], reg[f3], f2
19 4C00 111111444333-222 1 ZC sub reg[f4], reg[f3], reg[f2]
20 5000 1111113333332222 1 -- reg[f3] = f2
21 5400 111111444333-222 1 ZC adc reg[f4], reg[f3], reg[f2]
22 5800 1111114433332222 1 -- regpair[f4*2] = f3:f2
23 5C00 111111444333-222 1 ZC sbc reg[f4], reg[f3], reg[f2]
24 6000 1111114443332222 1 Z- and reg[f4], reg[f3], f2
25 6400 111111444333-222 1 Z- and reg[f4], reg[f3], reg[f2]
26 6800 1111114443332222 1 Z- or  reg[f4], reg[f3], f2
27 6C00 111111444333-222 1 Z- or  reg[f4], reg[f3], reg[f2]
28 7000 1111114443332222 1 Z- xor reg[f4], reg[f3], f2
29 7400 111111444333-222 1 Z- xor reg[f4], reg[f3], reg[f2]
30 7800 111111333333---- 1 -- regpair[f3] = M
31 7C00 111111333333---- 1 -- M = regpair[f3]
32 8000 1111444433332222 1 -- WRam[f4:f3] = f2
36 9000 1111222222222222 0 -- call
40 A000 1111222222222222 2 -- call, setting high nybble of PC to zero
44 B000 1111222222222222 1 -- jump if Z=1
48 C000 1111222222222222 1 -- jump if Z=0
52 D000 1111222222222222 1 -- jump if C=1
56 E000 1111222222222222 1 -- jump if C=0
60 F000 1111222222222222 1 -- jump, sets high nybble of PC to reg7 if previous instruction modified reg7

I notice the emulator has ROM and RAM as separate address spaces, so it can't execute code from RAM... let's hope that's not how the actual calculator works.

Edit: things don't look good; section 4.3 of that pdf shows ROM and RAM both starting from address 0.

Yeah what i'm thinking about doing right now is just straight up buying bitcoins since they're like going up 50 cents a day

Following the greater fool theory? Dangerous. This bubble will pop, we just don't know when.

Could someone please explain why this makes the coins of monetary value?

The way any currency has value is that you can buy things with it. The value is basically proportional to the amount of trade that takes place with the currency, divided by the amount of the currency in existence.

Bitcoin has a tightly controlled rate of creation (more people getting into it does not mean more bitcoins will be created), so the more people involved, the more valuable it gets. Once that gets as high as it's going to get, the 2009ers will cash out, making themselves rich, but causing a large drop in bitcoin value (due to the millions of "new" bitcoins entering circulation), which will very quickly turn into an outright crash (nobody wants to be stuck holding a currency that's rapidly dropping in value, so people will try to get out while they still can, causing a positive-feedback loop) - so everyone else is stuck holding now-worthless imaginary money.

A very long time

EDIT: I wondered what happened when it hit 0 difficulty?

Actually that wasn't the difficulty that hit 0 briefly, only the amount of mining.