Author Topic: TI-Nspire GB Emulator  (Read 150206 times)

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Offline calc84maniac

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Re: TI-Nspire GB Emulator
« Reply #90 on: December 08, 2009, 03:09:54 pm »
By the way, is the emulator's speed accurate? I mean, I added a delay loop of "loop subs r8,r8,#1 \ bne loop" when r8 contained 400,000, and that was for each of 60 frames. That loop should be 4 cycles per iteration, right? That adds up to delays of more than 90MHz, which doesn't add up.
It's not accurate. Right now, it just assumes all instructions are one cycle, or 1/90 microseconds. If your computer is not fast, it can lag, however. A tight loop like that is very likely to lag; I would recommend adding a few dozen repetitions of a simple instruction like "mov r0,r0" which nspire_emu can execute very fast.
Well, there wasn't an issue with lag, it was more an issue of the emulator running faster than expected.

Edit: Would more accurate cycle counting slow down the emulation significantly? (Aside from the fact that instructions would take longer)
« Last Edit: December 08, 2009, 03:25:38 pm by calc84maniac »
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Re: TI-Nspire GB Emulator
« Reply #91 on: December 08, 2009, 03:57:34 pm »
That Super Mario Bros. secrrnie was the coolest thing I've sceen all day.
You're doing an awesome job with this calc84!

Offline Goplat

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Re: TI-Nspire GB Emulator
« Reply #92 on: December 08, 2009, 04:17:14 pm »
Edit: Would more accurate cycle counting slow down the emulation significantly? (Aside from the fact that instructions would take longer)
That depends on what version of ARM the Nspire uses. The newer versions have longer pipelines, and the longer a CPU's pipeline is the more complicated it gets to predict how long something will take. Let's just hope it's not an ARM11 model.
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Offline calc84maniac

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Re: TI-Nspire GB Emulator
« Reply #93 on: December 08, 2009, 04:31:18 pm »
Edit: Would more accurate cycle counting slow down the emulation significantly? (Aside from the fact that instructions would take longer)
That depends on what version of ARM the Nspire uses. The newer versions have longer pipelines, and the longer a CPU's pipeline is the more complicated it gets to predict how long something will take. Let's just hope it's not an ARM11 model.
Hackspire says it has one of these

Edit: Found the cycle counts here. And my "load byte, look up address in table and branch" routine looks like it will take 9 clock cycles instead of the 2 the emulator currently does...
« Last Edit: December 08, 2009, 05:12:49 pm by calc84maniac »
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Offline miotatsu

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Re: TI-Nspire GB Emulator
« Reply #94 on: December 08, 2009, 08:25:18 pm »
so does this mean it will run slower on the actual calc then?

Offline calc84maniac

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Re: TI-Nspire GB Emulator
« Reply #95 on: December 08, 2009, 08:31:55 pm »
so does this mean it will run slower on the actual calc then?
Definitely slower than it has been running. No way to tell yet whether it will still run games fullspeed though.
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Offline Silver Shadow

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Re: TI-Nspire GB Emulator
« Reply #96 on: December 09, 2009, 12:56:58 am »
so does this mean it will run slower on the actual calc then?
Definitely slower than it has been running. No way to tell yet whether it will still run games fullspeed though.
Even without delay loops?
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Re: TI-Nspire GB Emulator
« Reply #97 on: December 09, 2009, 03:05:42 am »
I hope it runs at least faster than TI-Boy SE O.o, else it would mean the Nspire isn't that fast after all (altough I wonder if it couldn't just be because of the larger screen)

Offline Goplat

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Re: TI-Nspire GB Emulator
« Reply #98 on: December 09, 2009, 01:14:41 pm »
Edit: Found the cycle counts here.
Just as I feared, it has interlocks, so you can't just look at an instruction in isolation and say "this takes X cycles". The two-cycle interlock on ldrb/ldrh/ldrsh is particularly noxious. Consider this instruction sequence:

0: ldrcsb   r1,[r2]
4: muleq   r3,r4,r5
8: mov   r0,r1

If we enter at offset 8, this takes 1 cycle, of course.
If we enter at offset 4: If Z is set (mul executed), this takes 2 additional cycles, else 1. So, the translator must insert code along with the multiply to add an extra cycle. Not a big problem yet...
If we enter at offset 0: If C is clear (ldrb not executed), just 1 additional cycle, not a problem. But if C is set (ldrb executed), then the interlock adds a second additional cycle only if the mul is not executed! The number of cycles we have to attribute to the ldrcsb depends on both the C and Z flags even though the instruction itself has nothing to do with Z.

Thankfully interlocks never last through a taken branch instruction, so at least it's not necessary to keep any state between different code blocks. I think implementing those cycle timings is possible, but it would not be easy. I would rather wait until we're completely sure this is the kind of CPU the Nspire uses, before implementing it.
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Offline jsj795

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Re: TI-Nspire GB Emulator
« Reply #99 on: December 09, 2009, 01:32:46 pm »
I have no idea what you guys are talking about, but keep up the good work o.o
You guys are too advanced for me. I understand this is a hard work and appreciate it a lot ^^


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Offline calc84maniac

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Re: TI-Nspire GB Emulator
« Reply #100 on: December 09, 2009, 02:46:59 pm »
Maybe you can do something different with the register accesses on the couple of instructions afterward - basically on the load from memory you could do "interlockcount = cyclecount + 2" and upon register accesses, "if reg == loadedreg and interlockcount > cyclecount: cyclecount = interlockcount"
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Offline Goplat

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Re: TI-Nspire GB Emulator
« Reply #101 on: December 09, 2009, 03:33:09 pm »
Maybe you can do something different with the register accesses on the couple of instructions afterward - basically on the load from memory you could do "interlockcount = cyclecount + 2" and upon register accesses, "if reg == loadedreg and interlockcount > cyclecount: cyclecount = interlockcount"
If I made the translator actually emit code to do that I think it would slow emulation way down, with several real instructions added per emulated instruction. It needs to precompute cycle counts as much as possible.
« Last Edit: December 09, 2009, 03:38:40 pm by Goplat »
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Offline calc84maniac

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Re: TI-Nspire GB Emulator
« Reply #102 on: December 09, 2009, 04:01:02 pm »
Maybe you can do something different with the register accesses on the couple of instructions afterward - basically on the load from memory you could do "interlockcount = cyclecount + 2" and upon register accesses, "if reg == loadedreg and interlockcount > cyclecount: cyclecount = interlockcount"
If I made the translator actually emit code to do that I think it would slow emulation way down, with several real instructions added per emulated instruction. It needs to precompute cycle counts as much as possible.
Well actually, the "reg == loadedreg" part could be purely done in the translator - and if false, you don't even need to add any extra instructions. Also, since the interlocking will add extra cycles to the ARM instruction, I don't think the speed difference would be too costly...

And keep in mind that this solution only applies to the ldrb/ldrh opcodes, not ldr. In the ldr case, you can simply add an extra cycle to the following instruction if it accesses the loaded register.
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Offline Goplat

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Re: TI-Nspire GB Emulator
« Reply #103 on: December 09, 2009, 04:14:41 pm »
And keep in mind that this solution only applies to the ldrb/ldrh opcodes, not ldr. In the ldr case, you can simply add an extra cycle to the following instruction if it accesses the loaded register.
The extra cycle(s) on a pair of instructions affected by an interlock must be associated with the earlier instruction, not the later. Otherwise, they would erroneously be counted in the case that we branch directly to the later instruction, bypassing the earlier one.
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Offline calc84maniac

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Re: TI-Nspire GB Emulator
« Reply #104 on: December 09, 2009, 04:22:20 pm »
Okay, new idea. For ldrb/ldrh:
Set a flag during the load instruction.
For the second instruction, if it uses the loaded register and the flag is set, add an interlocking delay and reset the flag.
Otherwise, if it takes more than one cycle, reset the flag.
For the last instruction, if it uses the loaded register and the flag is set, add an interlocking delay.
Reset the flag.

Same idea for ldr except remove the case of the second instruction.
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